Semiconductor memory device having improved cell array layout

Semiconductor memory device having improved column selection str

Semiconductor memory device having improved column selection...

Semiconductor memory device having improved connections between

Semiconductor memory device having improved data output circuit

Semiconductor memory device having improved decoders for...

Semiconductor memory device having improved hierarchical I/O lin

Semiconductor memory device having improved write-verify operati

Semiconductor memory device having large data I/O width and...

Semiconductor memory device having layered bit line structure

Semiconductor memory device having level-shifted precharge signa

Semiconductor memory device having level-shifted precharge signa

Semiconductor memory device having level-shifted precharge signa

Semiconductor memory device having main word decoder skipping de

Semiconductor memory device having main word lines and sub word

Semiconductor memory device having memory architecture...

Semiconductor memory device having memory cell array divided int

Semiconductor memory device having memory cell block...

Semiconductor memory device having memory cell blocks...

Semiconductor memory device having memory cells reorganizable in