Semiconductor memory device having improved data output circuit

Details Semiconductor memory device having improved data output circuit Semiconductor memory device having improved data output circuit

1998-09-16

1999-11-23

Nelms, David

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

365194, G11C 800

Patent

active

059912286

ABSTRACT:
A data out circuit of a DRAM includes a normal operation determining part receiving a RASB (row address strobe bar) and a CASB (column address strobe bar) to determine whether a normal operation or an abnormal operation to be performed, a write/read determining part determining whether a read operation or a write operation to be performed, a first delaying part generating an OEC (out enable control) signal to delay a DOE (data output enable) generation signal, a controlling part outputting an EQSWB (equalizer switch bar) to control the DOE to transit only a first transit of the CASB, and a switching part receiving signals from the first delaying part and the controlling part, and switching the DOE, and a DOE generating part receiving signals from the normal operation recognizing part and the write/read determining part, and the switching part to generate the DOE signal outputting only a valid data.

REFERENCES:
patent: 4794567 (1988-12-01), Akatsuka
patent: 4894803 (1990-01-01), Aizaki
patent: 5353423 (1994-10-01), Hamid et al.
patent: 5526320 (1996-06-01), Zagar et al.
patent: 5673270 (1997-09-01), Tsujimoto
patent: 5815437 (1998-09-01), Pascucci et al.
patent: 5831908 (1998-11-01), Tsuji
patent: 5883851 (1999-03-01), Lee
patent: 5889707 (1999-03-01), Yang

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