Semiconductor memory device having memory cell blocks...

Details Semiconductor memory device having memory cell blocks... Semiconductor memory device having memory cell blocks...

1999-06-17

2001-05-22

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S200000, C365S051000, C365S052000

Reexamination Certificate

active

06236615

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a semiconductor memory device such as a dynamic random access memory device and, more particularly, to the layout of memory cell blocks incorporated in the semiconductor memory device.
DESCRIPTION OF THE RELATED ART
A typical example of the semiconductor dynamic random access memory device is shown in
FIG. 1
of the drawings. The prior art semiconductor dynamic random access memory device comprises memory cell sub-arrays
1
a
/
1
b
/
1
c
/
1
d
, row address decoders
2
a
/
2
b
and column address decoder/selector units
3
a
/
3
b
and sense amplifiers
4
a
/
4
b
. These components
1
a
-
1
d
/
2
a
-
2
b
/
3
a
-
3
b
/
4
a
-
4
b
are arranged on a semiconductor chip
5
as follows. Each of the memory cell sub-arrays
1
a
-
1
d
includes memory cells, word lines selectively connected to the memory cells and bit line pairs selectively connected to the memory cells. The memory cell is of the type having an access transistor and a storage capacitor connected in series. The word lines extend in the direction indicated by an arrow AR
1
, and the bit line pairs extend in a perpendicular direction to the word lines. The memory cell sub-arrays
1
a
/
1
b
/
1
c
/
1
d
are respectively assigned to areas of the semiconductor chip
5
, and the boundaries of each area extending in parallel to the word lines are hereinbelow referred to as “side lines” of the memory cell sub-array
1
a
/
1
b
/
1
c
/
1
d
. On the other hand, the other boundaries in parallel to the bit line pairs are referred to as “end lines” of the memory cell sub-arrays
1
a
/
1
/b/
1
c
/
1
d
. The memory cell sub-array
1
b
is contiguous to the memory cell sub-array
1
c
, and a side line is shared between the memory cell sub-arrays
1
b
and
1
c
. The other side lines of the memory cell sub-arrays
1
b
/
1
c
are spaced from the side lines of the memory cell sub-arrays
1
a
/
1
d
, and the areas between the memory cell sub-arrays
1
b
/
1
c
and the other memory cell sub-arrays
1
a
/
1
d
are assigned to the column address decoders/selectors/sense amplifiers
3
a
/
4
a
and
3
b
/
4
b
, respectively. The row address decoders
2
a
/
2
b
are assigned areas contiguous to the end lines of the memory cell sub-arrays
1
a
/
1
b
and the end lines of the memory cell sub-arrays
1
c
/
1
d
, respectively. The data storage capacity of the semiconductor dynamic random access memory device has been increased, and a shared-sense amplifier technology and a main-sub word line technology are employed in the semiconductor dynamic random access memory device. The shared sense amplifiers are provided on both ends of the memory cell sub-arrays, and selected one of the shared sense amplifiers increases the magnitude of a potential difference representative of a data bit read out from one of the memory cells forming a memory cell sub-array. The main-sub word line technology stepwise selects a row of memory cells from the memory cell sub-array. A row address predecoded signal is supplied to a main row address decoder, and the main address decoder selects one of the main word lines. Sub-decoders are selectively enabled through the main word lines, and the selected sub-decoder changes one of the sub-word lines to the active level in response to another row address predecoded signal. The rows of memory cells are respectively connected to sub-word lines, and data bits are read out from the row of memory cells connected to the selected sub-word line. Assuming now that the row address signal consists of (n+1) address bits X
0
, X
1
, X
2
, X
3
, . . . and Xn, the main row address decoder is responsive to the address bits X
3
−Xn so as to select one of the main word lines and the sub-decoder coupled to the selected main word line, and the selected sub-decoder is responsive to the address bits X
0
−X
2
so as to select a row of memory cells through the associated sub-word line. Thus, the main-sub word line technology stepwise selects the row of memory cells from the memory cell array, and the groups of sub-word lines divide the memory cell array into memory cell sub-arrays assigned areas parallel to one another.
FIG. 2
illustrates the layout of another semiconductor dynamic random access memory device. The shared sense amplifier technology and the main-sub word line technology are employed in the prior art semiconductor dynamic random access memory device. A memory cell array
10
is assigned a rectangular area on a semiconductor chip except a lattice-like area, and the memory cells MC are formed in small rectangular sub-areas as shown. The space over the small rectangular sub-area to be occupied by the memory cells MC is called as “plate space”.
A main row address decoder/a controller for sense amplifiers
11
are assigned an area contiguous to one of the end lines, and main word lines extends from the row address decoder
1
lover rows of plate spaces in the direction indicated by an arrow AR
2
. Sub-decoders SD are assigned narrow areas between the small rectangular areas of each row, and sub-word lines extend from each sub-decoder SD over the place spaces on both sides thereof as indicated by an arrows AR
3
.
A column address decoder
12
assigned an area contiguous to a side line of the memory cell array
10
, and bit line pairs (not shown) extend over the place spaces in a direction perpendicular to the word lines. Sense amplifiers SA are assigned narrow areas between the small rectangular areas in each column. As a result, two groups of sense amplifiers SA are provided in the narrow areas along both side lines of the small rectangular area, and two sub-decoders SD are provided in the narrow areas along both end lines of the small rectangular area. However, extremely small rectangular areas at the four corners of the small rectangular area are not occupied by the sense amplifiers nor the sub-decoder. The extremely small rectangular areas are marked with “x” in FIG.
2
.
Drivers for the sense amplifiers SA are assigned the extremely small rectangular areas. Thus, the sub-drivers SD, the sense amplifiers SA and the drivers for the sense amplifiers SA are distributed to the narrow areas around the small rectangular areas. This layout is appropriate to increase the memory cells MC, and is conducive to enhance the production yield, because the layout allows the manufacturer to widen the gap between the signal lines. The layout is hereinbelow referred to as “layout for a distributed function”.
The manufacturer who employs the layout for a distributed function is to decide how many columns of sub-decoders SD the memory cell array
10
requires. In other words, the manufacturer decides how many memory cell blocks MC the memory cell array
10
should be divided. The memory cell array
10
is assumed to be 2
l
×2
m
bit dynamic random access memory cell array as shown in FIG.
3
. The row of 2
m
bit memory cells is divided into 2
m-n
memory cell blocks MC, and 2
n
memory cells form a row of memory cells in the memory cell block MC. The layout of memory cell blocks MC makes the plate spaces equal to one another. The manufacturer optimizes “n” from two viewpoints, i.e., the rectangular area occupied by the memory cell array
10
and an access to data stored in the memory cells. If “n” is increased, the sub-decoders SD are also increased, and a wide rectangular area is required for the memory cell array
10
. However, the access speed is got better. Because, the load to each sub-decoder SD is decreased, and the driver circuits for the sense amplifiers are increased. On the other hand, if “n” is decreased, the sub-decoders SD and the driving circuits for the sense amplifiers SA are decreased. The rectangular area required for the memory cell array
10
becomes narrow. However, the load is increased, and the access speed is got worse.
Using the layout for a distributed function shown in
FIG. 3
, a manufacturer may arrange dynamic random access memory cell blocks MC in a layout shown in FIG.
4
. Two rectangular areas on a semiconductor chip
20
are respectively assigned to two memo

Affiliated with

Also associated with

Rating

Semiconductor memory device having memory cell blocks... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device having memory cell blocks..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having memory cell blocks... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2529404