Semiconductor memory device having memory cell array divided int

Details Semiconductor memory device having memory cell array divided int Semiconductor memory device having memory cell array divided int

1997-07-25

1998-11-10

Yoo, Do Hyun

Static information storage and retrieval

Addressing

Plural blocks or banks

36518905, 365193, G11C 700

Patent

active

058354379

ABSTRACT:
An internal control signal generating circuit produces first and second control signals according to input signals received from a /RAS pin, a first /CAS pin, and a second /CAS pin. Upon readout operation, readout data of first or second memory block is output from a first external terminal while readout data of third or fourth memory block is output from a second external terminal according to the first and second control signals. Meanwhile, upon write operation, input data from the first external terminal becomes write data of first or second memory block while input data from the second external terminal becomes write data of third or fourth memory block according to first and second control signals. Accordingly, it is possible to suppress increase in the chip area caused from increase in number of memory blocks.

REFERENCES:
patent: 5621695 (1997-04-01), Tran
patent: 5627791 (1997-05-01), Wright et al.
patent: 5629902 (1997-05-01), Hoshi et al.
patent: 5638335 (1997-06-01), Akiyama et al.
patent: 5691955 (1997-11-01), Yamauchi

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