Second-order highpass difference filter
Secure and fast calculating unit
Secure asynchronous clock multiplexer
Secured master-slave D type flip-flop circuit
Segmented dual delay-locked loop for precise variable-phase cloc
Select signal generating circuit having clamp circuit for...
Selectability of maximum magnitudes for K-winner take all...
Selectable clock generation mode
Selectable equalization system and method
Selectable equalization system and method
Selectable input attenuation
Selectable low power signal line and method of operation
Selectable pole bias line filter
Selectable pole bias line filter
Selectable resistor and/or driver for an integrated circuit...
Selectable single ended-to differential output adjustment...
Selectable timing delay system
Selectably boosted control signal based on supply voltage
Selecting a bias for a level shifting device
Selecting a bias for a level shifting device