Selectable clock generation mode

Details Selectable clock generation mode Selectable clock generation mode

1995-12-15

1999-07-20

Lan, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

327291, 327150, 327159, 395556, 395558, G06F 106

Patent

active

059260530

ABSTRACT:
A processing system includes circuitry and methodology for selecting clock generation modes between phase-locked loop and static delay line loop circuitries. The node may be selectable through an externally accessible pin, an internal bond wire option, a boundary test scan control point, or other programmable register or control point.

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