Secure asynchronous clock multiplexer

Details Secure asynchronous clock multiplexer Secure asynchronous clock multiplexer

2000-02-08

2003-03-18

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Converging with plural inputs and single output

C327S298000

Reexamination Certificate

active

06535048

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to clock systems and, in particular, to an improved clock multiplexer.
2. Description of the Related Art
Many digital electronic devices require flexible clock management that allows switching between different clock sources and/or frequencies while the device remains operational. For example, power consumption can be optimized by using the maximum clock frequency only for processing of time critical tasks while a slower clock is applied to the system for other tasks. Typically, a clock multiplexer is employed to select between multiple clocks.
FIG. 1
illustrates such a clock multiplexer circuit. As shown in
FIG. 1
, a multiplexer
102
is provided which receives a CLK
0
and a CLK
1
input. The CLK
0
input is output from a clock divider
104
. A select signal SELECT is used to select between CLK
0
and CLK
1
.
Any implementation of a clock multiplexer should guarantee that the duration of the multiplexed clock outputs remain intact (undistorted) and that the multiplexed clock is spike free. This is accomplished relatively easily if the select signal SELECT is synchronous to both source clocks. In
FIG. 1
, the two alternate clocks are synchronous to one another, so synchronizing the select signal is relatively straightforward. However, if the two alternate clocks are asynchronous to one another, a simple combinatorial multiplexer, as shown in
FIG. 1
, no longer generates a spike-free undistorted clock. But even in the case where both clocks are synchronous, the potential variations in the intrinsic and interconnect delays of the circuit components are much easier to deal with during physical implementation if no fixed relation is imposed on the arrival times of the clocks at the multiplexer.
Turning now to
FIG. 2
, a diagram of an exemplary known clock multiplexer is shown. The clock multiplexer
200
receives clock inputs CLK
0
and CLK
1
, and a select input SELECT. The clock multiplexer
200
includes a pair of cross coupled clock gating elements
202
a,
202
b.
As shown, each gating element
202
a,
202
b
includes a flip flop
204
a,
204
b,
an AND gate
208
a,
208
b
and an inverter
206
a,
206
b.
Clock inputs CLK
0
, CLK
1
are provided to the inverters
206
a,
206
b,
respectively. The flip flops
204
a,
204
b
receive enable signals EN
0
and EN
1
, respectively, and output enable signals CLK
0
_EN and CLK
1
_EN, respectively. By control of the enable signals CLK
0
_EN, CLK
1
_EN, the input clocks CLK
0
, CLK
1
are either passed through the AND gates
208
a,
208
b,
respectively, or the outputs of the AND gates GC
0
, GC
1
, are forced to 0. The clock gating elements
202
a,
202
b
are coupled by way of AND gates
210
,
212
and output OR gate
214
. The AND gate
210
has two inverting inputs; the AND gate
212
has a single inverting input. On change of the select signal, the previously selected clock is disabled before the newly selected clock is enabled.
In particular, the SELECT signal is inverted at the input of the AND gate
210
, but not the AND gate
212
, such that SELECT will be clocked through only one or the other of the clock gating elements. Further, the output CLK
1
_EN of the flip flop
204
b
is fed back to the inverting input of the AND gate
210
. The output CLK
0
_EN of the flip flop
204
a
is fed back to the inverting input of the AND gate
212
. Thus, the enable signal EN
0
is output from the AND gate
210
when the SELECT is low and the previous CLK
1
_EN is also low or inactive. Similarly, the enable EN
1
is clocked through the flip flop
204
b
when the SELECT signal is high and the previous CLK
0
_EN is also inactive. A known variation of the circuit of
FIG. 2
is to employ a pair of cascaded flip flops in each gating element.
While the circuit of
FIG. 2
is generally effective in producing a clean switched clock, relative care must be taken to ensure that the select signal SELECT does not change without a clock being enabled and when both clocks have a falling edge near the same time. In such cases, one flip flop might latch the old value of select while the other is already latching the new value. This can result in both clocks being simultaneously enabled. For example,
FIG. 3
is a timing diagram of the circuit of FIG.
2
. Illustrated are the CLK
0
waveform
350
, CLK
1
waveform
352
, SELECT waveform
354
, SELECT
0
waveform
356
, SELECT
1
waveform
358
, CLK
0
_EN waveform
360
, CLK
1
_EN waveform
362
, and CLK waveform
364
. As shown, the CLK waveform
364
has a spike
301
when both clocks CLK
0
_EN and CLK
1
_EN are enabled.
SUMMARY OF THE INVENTION
These and other drawbacks in the prior art are overcome in large part by a system and method for clock multiplexing according to the present invention. According to one implementation, a pair of two-stage cross-coupled clock gating elements are controlled by a single asynchronous enable signal. On change of the enable signal, the previously selected clock always gets disabled before the newly selected clock is enabled.


REFERENCES:
patent: 4853653 (1989-08-01), Maher
patent: 5289050 (1994-02-01), Ogasawara
patent: 5726593 (1998-03-01), Ruuskanen
patent: 6275546 (2001-08-01), Miller et al.
patent: 0 969 350 (2000-01-01), None

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