Reconfigurable SIMD coprocessor architecture for sum of...

Reconfigurable vector-FFT/IFFT, vector-multiplier/divider

Rectifying transfer gate circuit

Recursive carry-select topology in incrementer designs

Recursive digital filter with reset

Recursive lookahead-based 2.sup.n -bit serial multipliers over G

Recursive state estimation by matrix factorization

Recursively partitioned carry select adder

Reduced complexity adaptive filter

Reduced complexity and increased flexibility modified fast...

Reduced complexity fast hadamard transform

Reduced complexity IDCT decoding with graceful degradation

Reduced computation digital filter

Reduced computation system for wavelet transforms

Reduced gate count differentiator

Reduced hardware linear interpolator

Reduced multiplier digital IIR filters

Reduced power matched filter using precomputation

Reduced product term carry chain

Reduced-hardware soft error detection