Recursive lookahead-based 2.sup.n -bit serial multipliers over G

Details Recursive lookahead-based 2.sup.n -bit serial multipliers over G Recursive lookahead-based 2.sup.n -bit serial multipliers over G

1998-04-16

2000-03-28

Ngo, Chuong Dinh

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

G06F 700

Patent

active

060443901

ABSTRACT:
The present invention is a 2.sup.n -bit serial multiplier design optimized for both speed and silicon area. The multiplier design includes source registers, recursive multiplication logic, and destination registers. According to the method of the present invention, the 2.sup.n -bit serial multiplier design is implemented by performing a precomputing (cycle-stealing) step in which source registers are preloaded with the recursively reconstructed and zero-padded input data and the designation registers are preloaded with zeros or the highest input field coefficient while the first cycle of the multiplication phase is taking place.

REFERENCES:
patent: 4251875 (1981-02-01), Marver et al.
patent: 4797848 (1989-01-01), Walby
patent: 5742530 (1998-04-01), Gressel et al.
patent: 5818855 (1998-10-01), Foxcroft

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