Selected register decode values for pipeline stage register...
Selecting multiple threads for substantially concurrent...
Selecting register or previous instruction result bypass as sour
Selective canonizing on mode transitions
Selective execution of deferred instructions in a processor...
Selective flush of shared and other pipeline stages in a...
Selective suppression of register renaming
Selective vertical and horizontal dependency resolution via...
Selectively deferring instructions issued in program order...
Selectively powered retirement unit using a partitioned...
Shared dependency checking for status flags
Shared resource queue for simultaneous multithreading...
Simple load and store disambiguation and scheduling at...
Simple load and store disambiguation and scheduling at...
Simultaneously assigning corresponding entry in multiple...
SMT flush arbitration
Software controllable register map
Special instruction register including allocation field utilized
Speculation pointers to identify data-speculative operations...
Speculative counting of performance events with rewind counter