Renaming registers to values produced by instructions...

Reorder buffer which forwards operands independent of storing de

Reservation stations to increase instruction level parallelism

Resolving dependencies among concurrently dispatched...

Resource management using multiply pendent registers

Retaining flag value associated with dead result data in...

Scoreboard mechanism for serialized string operations...

Selective canonizing on mode transitions

Selective suppression of register renaming

Shared dependency checking for status flags

Shared resource queue for simultaneous multithreading...

Software controllable register map

Special instruction register including allocation field utilized

Speculative execution of a load instruction by associating...

Speculative instructions exection in VLIW processors

Speculative renaming of data-processor registers

Split data-flow scheduling mechanism

Substitute register for use in a high speed data processor

Superscalar processor having content addressable memory...

Suppressing register renaming for conditional instructions...