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Reduced pin system interface

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Reduced synchronization reservation system and method for a...

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
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Reducing ABENDS through the use of second-tier storage groups

Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – Dynamic-type storage device
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Reducing bandwidth and areas needed for non-inclusive memory hie

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent

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Reducing bus width by data compaction

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
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Reducing cache misses by snarfing writebacks in non-inclusive me

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Reducing cache pollution of a software controlled cache

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Reducing communication for reads and updates in distributed...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Reducing content addressable memory (CAM) power consumption...

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Reducing content addressable memory (CAM) power consumption...

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Reducing data copy operations for writing data from a...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Reducing delay of command completion due to overlap condition

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Reducing disk IO by full-cache write-merging

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Reducing inventory after media access in an automated data...

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Reducing latency for a relocation cache lookup and address...

Electrical computers and digital processing systems: memory – Address formation – Address mapping
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Reducing latency of a snoop tenure

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Reducing load imbalance in a storage system

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Reducing memory access latencies from a bus using...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Reducing memory fragmentation

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
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Reducing memory latency by not performing bank conflict...

Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
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