Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-12-13
2005-12-13
Chace, Christian P. (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
06976132
ABSTRACT:
A method and system for reducing latency of a snoop tenure. A bus macro may receive a snoopable transfer request. The bus macro may determine which snoop controllers in a system will participate in the snoop transaction. The bus macro may then identify which participating snoop controllers are passive. Passive snoop controllers are snoop controllers associated with cache memories with cache lines only in the shared or invalid states of the MESI protocol. The snoop request may then be completed by the bus macro without waiting to receive responses from the passive participating snoop controllers. By not waiting for responses from passive snoop controllers, the bus macro may be able to complete the snoop request in a shorter amount of time thereby reducing the latency of the snoop tenure and improving performance of the system bus.
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Dieffenderfer James N.
Drerup Bernard C.
Ganasan Jaya P.
Hofmann Richard G.
Sartorius Thomas A.
Chace Christian P.
International Business Machines - Corporation
Voigt, Jr. Robert A.
Winstead Sechrest & Minick PC
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