Reducing memory access latencies from a bus using...

Details Reducing memory access latencies from a bus using... Reducing memory access latencies from a bus using...

2006-08-08

2006-08-08

Padmanabhan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S154000, C711S133000, C711S159000, C707S793000

Reexamination Certificate

active

07089367

ABSTRACT:
The present invention is a method and apparatus to reduce latency in accessing a memory from a bus. The apparatus comprises a pre-fetcher and a cache controller. The pre-fetcher pre-fetches a plurality of data from the memory to a cache queue in response to a request. The cache controller is coupled to the cache queue and the pre-fetcher to deliver the pre-fetched data from the cache queue to the bus in a pipeline chain independently of the memory.

REFERENCES:
patent: 5309451 (1994-05-01), Noya et al.
patent: 5408644 (1995-04-01), Schneider et al.
patent: 5542058 (1996-07-01), Brown, III et al.
patent: 5724613 (1998-03-01), Wszolek
patent: 5802569 (1998-09-01), Genduso et al.
patent: 5867683 (1999-02-01), Witt et al.
patent: 6216208 (2001-04-01), Greiner et al.
patent: 6356962 (2002-03-01), Kasper
Microsoft Press, Computer Dictionary (Third edition).

Affiliated with

Also associated with

Rating

Reducing memory access latencies from a bus using... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Reducing memory access latencies from a bus using..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reducing memory access latencies from a bus using... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3608698