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Multiple changeable addressing mapping circuit

Electrical computers and digital processing systems: memory – Address formation – Combining two or more values to create address
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Multiple client memory arbitration system capable of operating m

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Multiple computer system with enhanced memory clean up

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Multiple consumer-multiple producer rings

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Multiple contexts for efficient use of translation lookaside...

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Multiple contexts for efficient use of translation lookaside...

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Multiple data management method, computer and storage device...

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Multiple device data transfer utilizing a multiport memory with

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Multiple disk data storage system for reducing power...

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Multiple entry wavetable address cache to reduce accesses over a

Electrical computers and digital processing systems: memory – Address formation – Combining two or more values to create address
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Multiple erase block tagging in a flash memory device

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Multiple independent coherence planes for maintaining coherency

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Multiple independent coherence planes for maintaining coherency

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Multiple independent levels of security (MILS) certifiable...

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Multiple input two-level cache directory with mini-directory for

Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – Addressing cache memories
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Multiple issue algorithm with over subscription avoidance...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Multiple level cache control system with address and data pipeli

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Multiple level cache memory with overlapped L1 and L2 memory acc

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Multiple load miss handling in a cache memory system

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Multiple machine architecture with overhead reduction

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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