Multiple erase block tagging in a flash memory device

Details Multiple erase block tagging in a flash memory device Multiple erase block tagging in a flash memory device

2006-07-10

2009-11-17

Bragdon, Reginald G (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

Reexamination Certificate

active

07620768

ABSTRACT:
A plurality of memory devices can be erase block tagged in parallel by issuing an erase pulse to memory devices that do not have memory blocks with erase block latches that indicate the block is erased. The status of the memory block is read after the erase pulse. If there are blocks remaining to be erased, erase block tag patterns are generated. Each memory block at a particular sector address has a unique erase block tag pattern to set the erase block latch for that particular memory block. The patterns are transmitted in parallel to the memory devices in a data burst.

REFERENCES:
patent: 6055184 (2000-04-01), Acharya
patent: 6529416 (2003-03-01), Bruce et al.
patent: 6577540 (2003-06-01), Choi
patent: 6643184 (2003-11-01), Pio
patent: 6735119 (2004-05-01), Mihara

Affiliated with

Also associated with

Rating

Multiple erase block tagging in a flash memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiple erase block tagging in a flash memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiple erase block tagging in a flash memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4130800