Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Patent
1997-11-05
1999-11-02
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
711150, 711168, G06F 1314
Patent
active
059788895
ABSTRACT:
A quad-port random access memory (RAM) is accessed simultaneously by a input-output (I/O) device, a digital signal processor (DSP), and a system bus with no need for any request/granted handshake. The I/O device, DSP, and system bus all constitute respectively different data transferring devices. The RAM is provided with three memory pages which are rotated logically by 120 degrees during successive time slots. The first memory page is accessed by the I/O device, the second memory page is accessed by the DSP, and the third memory page is accessed by the system bus during a first time slot. During subsequent time slots, the memory pages of the RAM are rotated logically so that data transfer is stepped through a predetermined sequence of data transferring device and memory page combinations in successive time slots so that all three data transferring devices are permitted to access the RAM at all times. The sequence continues repetitively during subsequent time slots. Data transmission and reception use opposite rotation directions and opposite device and memory page combinations.
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Ardis Robert B.
Cabeca John W.
Chow Christopher S.
Ostroff Irwin
Timeplex, Inc.
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