Multiple level cache memory with overlapped L1 and L2 memory acc

Details Multiple level cache memory with overlapped L1 and L2 memory acc Multiple level cache memory with overlapped L1 and L2 memory acc

1998-04-13

2000-10-24

Yoo, Do Hyun

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711117, 711118, 711119, 711150, 711 3, G06F 1208

Patent

active

061382086

ABSTRACT:
A method of providing simultaneous, or overlapped, access to multiple cache levels to reduce the latency penalty for a higher level cache miss. A request for a value (data or instruction) is issued by the processor, and is forwarded to the lower level of the cache before determining whether a cache miss of the value has occurred at the higher level of the cache. In the embodiment wherein the lower level is an L2 cache, the L2 cache may supply the value directly to the processor. Address decoders are operated in parallel at the higher level of the cache to satisfy a plurality of simultaneous memory requests. One of the addresses (selected by priority logic based on hit/miss information from the higher level of the cache) is gated by a multiplexer to a plurality of memory array word line drivers of the lower level of the cache. Some bits in the address which do not require virtual-to-real translation can be immediately decoded.

REFERENCES:
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patent: 5778422 (1998-07-01), Genduso et al.
patent: 5826052 (1998-10-01), Stiles et al.

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