Multiple level cache control system with address and data pipeli

Details Multiple level cache control system with address and data pipeli Multiple level cache control system with address and data pipeli

1994-11-15

2000-02-01

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711150, 711168, 711169, 711122, G06F 938

Patent

active

060214716

ABSTRACT:
A cache controller for a system having first and second level cache memories. The cache controller has multiple stage address and data pipelines. A look-up system allows concurrent look-up of tag addresses in the first and second level caches using the address pipeline. The multiple stages allow a miss in the first level cache to be moved to the second stage so that the latency does not slow the look-up of a next address in the first level cache. A write data pipeline allows the look-up of data being written to the first level cache for current read operations. A stack of registers coupled to the address pipeline is used to perform multiple line replacements of the first level cache memory without interfering with current first level cache memory look-ups.

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