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Latency tolerant distributed shared memory multiprocessor...

Electrical computers and digital processing systems: memory – Address formation – Address mapping
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Latency-aware replacement system and method for cache memories

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Latency-aware thread scheduling in non-uniform cache...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Layered local cache mechanism with split register load bus...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Layered local cache with imprecise reload mechanism

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Layered local cache with lower level cache optimizing...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Layered local cache with lower level cache updating upper...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Layered memory architecture for deterministic finite...

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
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Layered memory architecture for deterministic finite...

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
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Layout synopsizing process for efficient layout parasitic...

Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – Addressing cache memories
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Lazy deregistration protocol for a split socket stack

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
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Lazy flushing of translation lookaside buffers

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Lazy flushing of translation lookaside buffers

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Leaky cache mechanism

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Leasing scheme for data-modifying operations

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Least critical used replacement with critical cache

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Least frequently used eviction implementation

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Least mean square dynamic cache-locking

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Least mean square dynamic cache-locking

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Least recently used block replacement for four block cache logic

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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