Least mean square dynamic cache-locking

Details Least mean square dynamic cache-locking Least mean square dynamic cache-locking

2006-11-07

2006-11-07

Verbrugge, Kevin (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S152000, C711S163000

Reexamination Certificate

active

07133970

ABSTRACT:
A dynamic cache-locking algorithm may determine the most frequently used function(s) and the number of cache lines that should be locked into the instruction cache embedded into a processor. By evaluating the dynamic cache-locking algorithm, a determination may be made to lock an optimal amount of functions that correspond to a given, limited amount of instruction cache.

REFERENCES:
patent: 5249286 (1993-09-01), Alpert et al.
patent: 5875464 (1999-02-01), Kirk
patent: 6178482 (2001-01-01), Sollars
patent: 09034792 (1997-02-01), None

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