Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Reexamination Certificate
2002-07-11
2004-11-23
Padmanabhan, Mano (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
C711S203000, C710S022000, C702S010000
Reexamination Certificate
active
06823437
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to communication protocols between a host computer and an input/output (I/O) device. More specifically, the present invention provides a method by which previously registered memory can be reused through the use of a timer without requiring the registration of another memory region.
2. Description of Related Art
In an Internet Protocol (IP) Network, the software provides a message passing mechanism that can be used to communicate with input/output devices, general purpose computers (host), and special purpose computers. The message passing mechanism consists of a transport protocol, an upper level protocol, and an application programming interface. The key standard transport protocols used on IP networks today are the Transmission Control Protocol (TCP) and the User Datagram Protocol (UDP). TCP provides a reliable service and UDP provides an unreliable service. In the future the Stream Control Transmission Protocol (SCTP) will also be used to provide a reliable service. Processes executing on devices or computers access the IP network through upper level protocols, such as Sockets, iSCSI, and Direct Access File System (DAFS).
Unfortunately, the TCP/IP software consumes a considerable amount of processor and memory resources. This problem has been covered extensively in the literature (see J. Kay, J. Pasquale, “Profiling and reducing processing overheads in TCP/IP”, IEEE/ACM Transactions on Networking, Vol 4, No. 6, pp.817-828, December 1996; and D. D. Clark, V. Jacobson, J. Romkey, H. Salwen, “An analysis of TCP processing overhead”, IEEE Communications Magazine, volume: 27, Issue: 6, June 1989, pp 23-29). In the future the network stack will continue to consume excessive resources for several reasons, including: increased use of networking by applications; use of network security protocols; and the underlying fabric bandwidths are increasing at a higher rate than microprocessor and memory bandwidths. To address this problem the industry is offloading the network stack processing to an IP Suite Offload Engine (IPSOE).
There are two offload approaches being taken in the industry. The first approach uses the existing TCP/IP network stack, without adding any additional protocols. This approach can offload TCP/IP to hardware, but unfortunately does not remove the need for receive side copies. As noted in the papers above, copies are one of the largest contributors to central processing unit (CPU) utilization. To remove the need for copies, the industry is pursuing the second approach that consists of adding Framing, Direct Data Placement (DDP), and Remote Direct Memory Access (RDMA) over the TCP and SCTP protocols. The IP Suite Offload Engine (IPSOE) required to support these two approaches is similar, the key difference being that in the second approach the hardware must support the additional protocols.
The IPSOE provides a message passing mechanism that can be used by sockets, iSCSI, and DAFS to communicate between nodes. Processes executing on host computers, or devices, access the IP network by posting send/receive messages to send/receive work queues on an IPSOE. These processes also are referred to as “consumers”.
The send/receive work queues (WQ) are assigned to a consumer as a queue pair (QP). The messages can be sent over four different transport types: traditional TCP, RDMA TCP, UDP, or SCTP. Consumers retrieve the results of these messages from a completion queue (CQ) through IPSOE send and receive work completion (WC) queues. The source IPSOE takes care of segmenting outbound messages and sending them to the destination. The destination IPSOE takes care of reassembling inbound messages and placing the inbound messages in the memory space designated by the destination's consumer. These consumers use IPSOE verbs to access the functions supported by the IPSOE. The software that interprets verbs and directly accesses the IPSOE is known as the IPSO interface (IPSOI).
Today, the host CPU performs most IP suite processing. IP Suite Offload Engines offer a higher performance interface for communicating to other general purpose computers and I/O devices. Data sends or receives through the IPSOE require that the CPU either copy data from one memory location to another or register the memory so that the IPSOE can directly access the memory region. Each of these options requires significant CPU resources with the memory registration option being preferred for large memory transfers; however, as network speeds increase the amount of CPU resources required will increase. It would be advantageous to have an improved method, apparatus, and computer instructions for reducing the amount of CPU resources required to register these memory locations.
SUMMARY OF THE INVENTION
The present invention provides a method, computer program product, and distributed data processing system for lazy deregistration of memory regions. Specifically, the present invention is directed to memory regions that are written to and from by an Integrated Protocol Suite Offload Engine (IPSOE) in accordance with a preferred embodiment of the present invention. A mechanism is provided for lazy deregistration of memory regions once the region is no longer required for a specific data transfer being carried out by the IPSOE. Rather than deregistering a memory region after a data transfer has been carried out, the memory region remains registered for some selected period of time. After that selected period of time passes, the region is then deregistered. If a second data transfer using this memory region occurs while the memory region is still registered, the registration overhead is avoided for this second data transfer. This mechanism reduces the amount of CPU resources required for transferring data by allowing reuse of previously registered memory regions.
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Intel, “Offload Sockets Framework and Sockets Direct Protocol High Level Design”, Jun. 2002, p. 2-1, (5-18)-(5-19).*
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Dubnicki et al, “Software Support for Virtual Memory-Mapped Comumication”, 1996, Proc of IPPS '96, p. 372-381.
Boyd William Todd
Joseph Douglas J.
Recio Renato John
Baker Paul A
International Business Machines - Corporation
Padmanabhan Mano
Salys Casimer K.
Yee Duke W.
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