Least recently used block replacement for four block cache logic

Details Least recently used block replacement for four block cache logic Least recently used block replacement for four block cache logic

1995-08-29

1998-04-07

Robertson, David L.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

G06F 1300

Patent

active

057377537

ABSTRACT:
In a high speed main frame computer system, a high speed instruction processor is provided with a high speed cache memory. The cache memory is provided with a plurality of associated memories including a tag memory. Every time the instruction processor attempts to access the cache memory, a cache set address is generated which accesses the associated memories to provide most recently used (MRU) block information, validity information and degrade block information. The accessed information is applied as inputs to a cache logic system. The cache logic system logically modifies the information to generate an update of the MRU information and writes the modified MRU information into the MRU associated memory at the set address without control or supervision on the part of the instruction processor. The cache logic system also generates the least recently used (LRU) block coded information using the MRU information, validity information and degraded block information for cache block replacement.

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