Latency-aware thread scheduling in non-uniform cache...

Details Latency-aware thread scheduling in non-uniform cache... Latency-aware thread scheduling in non-uniform cache...

2006-07-21

2009-08-11

Nguyen, Than (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S119000

Reexamination Certificate

active

07574562

ABSTRACT:
A system and method for latency-aware thread scheduling in non-uniform cache architecture are provided. Instructions may be provided to the hardware specifying in which banks to store data. Information as to which banks store which data may also be provided, for example, by the hardware. This information may be used to schedule threads on one or more cores. A selected bank in cache memory may be reserved strictly for selected data.

REFERENCES:
patent: 4445172 (1984-04-01), Peters et al.
patent: 5210843 (1993-05-01), Ayers
patent: 5875470 (1999-02-01), Dreibelbis et al.
patent: 6578065 (2003-06-01), Aglietti et al.

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