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Concentrated parity technique for handling double failures...

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Concentrated parity technique for handling double failures...

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Concurrent access of an unsegmented buffer by writers and...

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Concurrent access scheme for exclusive mode cache

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Concurrent configuration of drives of a data storage library

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
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Concurrent data recall in a hierarchical storage environment...

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Concurrent data restore and background copy operations in...

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Concurrent evacuation of the young generation

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Concurrent execution of critical sections by eliding...

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Concurrent execution of critical sections by eliding...

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Concurrent incremental garbage collector with a card table...

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Concurrent multi-processor memory testing beyond 32-bit...

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
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Concurrent non-blocking FIFO array

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
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Concurrent page tables

Electrical computers and digital processing systems: memory – Address formation – Address mapping
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Concurrent read access and exclusive write access to data in...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Concurrent switch to shadowed device for storage controller and

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Concurrent write of multiple chunks of data into multiple subarr

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Concurrent write of multiple chunks of data into multiple subarr

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Conditional data pre-fetching in a device controller

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Conditional early data address generation mechanism for a microp

Electrical computers and digital processing systems: memory – Address formation – Address mapping
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