Concurrent write of multiple chunks of data into multiple subarr

Details Concurrent write of multiple chunks of data into multiple subarr Concurrent write of multiple chunks of data into multiple subarr

1999-01-06

2000-12-05

Thai, Tuan V.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

711102, 711154, 365120, 36518905, 365222, G06F 1200

Patent

active

061579831

ABSTRACT:
An EEPROM system includes flash EEPROM cells organized into subarrays. Pairs of subarrays share row address decoders by sharing word lines, and individual subarrays have dedicated column address decoders and data registers. Each row decoder has an associated row address latch, and each column decoder has an associated column address latch. Multiple data chunks are concurrently written into the subarrays by first latching chunk addresses into the row and column address latches, and corresponding chunks of data into the data registers, then activating a programming signal to initiate concurrent programming and verifying the programming of the data chunks.

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