Electrical computers and digital processing systems: memory – Address formation – Address mapping
Patent
1996-07-24
1998-09-22
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Address formation
Address mapping
711202, 711213, 711214, 711215, 395383, 395387, G06F 926
Patent
active
058130454
ABSTRACT:
An apparatus is provided, including one or more early address generation units which attempt to perform data address generation upon decode of an instruction which includes a memory operand. The early address generation units may be successful at generating the data address if the logical data address is formed from a displacement only. Additionally, the early address generation unit may be successful at generating the data address if the logical data address is formed from the displacement and register operands which are available upon decode of the instruction. Data address generation latency may be shortened. If register operands are employed for forming the address and the register operands are not available, the data address may be generated in a functional unit at the execute stage. Therefore, the early address generation mechanism is a conditional mechanism which provides the data address early if the operands are available, and which provides the data address in a more conventional fashion if the operands are not available. In one embodiment, the early address generation units add the displacement value to the segment base address corresponding to the segment register selected by the instruction. The displacement/segment base address addition may be performed while awaiting register operands.
REFERENCES:
patent: 4044338 (1977-08-01), Wolf
patent: 4373182 (1983-02-01), Schultz et al.
patent: 4409654 (1983-10-01), Wada et al.
patent: 4453212 (1984-06-01), Gaither et al.
patent: 4807115 (1989-02-01), Torng
patent: 4855105 (1989-08-01), Kuriyama et al.
patent: 4858105 (1989-08-01), Kuriyama et al.
patent: 5168557 (1992-12-01), Shibuya
patent: 5226126 (1993-07-01), McFarland et al.
patent: 5226130 (1993-07-01), Favor et al.
patent: 5517657 (1996-05-01), Rodgers et al.
patent: 5519841 (1996-05-01), Sager et al.
patent: 5546593 (1996-08-01), Kimura et al.
patent: 5568630 (1996-10-01), Killian et al.
Intel, "Chapter 2: Microprocessor Architecture Overview," pp. 2-1 through 2-4.
Michael Slater, "AMD's K5 Designed to Outrun Pentium," Microprocessor Report, vol. 8, No. 14, Oct. 24, 1994, 7 pages.
Sebastian Rupley and John Clyman, "P6: The Next Step?," PC Magazine, Sep. 12,1995, 16 pages.
Tom R. Halfhill, "AMD K6 Takes On Intel P6," BYTE, Jan. 1996, 4 pages.
Mahalingaiah Rupaka
Tran Thang M.
Witt David B.
Advanced Micro Devices , Inc.
Chan Eddie P.
Kivlin B. Noel
Nguyen Than V.
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