Concurrent execution of critical sections by eliding...

Details Concurrent execution of critical sections by eliding... Concurrent execution of critical sections by eliding...

2006-10-10

2006-10-10

Bataille, Pierre (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

C711S151000, C711S152000

Reexamination Certificate

active

07120762

ABSTRACT:
Critical sections of multi-threaded programs, normally protected by locks providing access by only one thread, are speculatively executed concurrently by multiple threads with elision of the lock acquisition and release. Upon a completion of the speculative execution without actual conflict as may be identified using standard cache protocols, the speculative execution is committed, otherwise the speculative execution is squashed. Speculative execution with elision of the lock acquisition, allows a greater degree of parallel execution in multi-threaded programs with aggressive lock usage.

REFERENCES:
patent: 5421022 (1995-05-01), McKeen et al.
patent: 6684398 (2004-01-01), Chaudhry et al.
patent: 2002/0178349 (2002-11-01), Shibayama et al.
patent: 2003/0014473 (2003-01-01), Ohsawa et al.
patent: 2003/0014602 (2003-01-01), Shibayama et al.

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