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Matching memory transactions to cache line boundaries

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Mathematical morphology processing method

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Maximal concurrent lookup cache for computing systems having a m

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Maximizing hit ratio in an automated storage library

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Maximizing sequential output in a disk array storage device

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Maximizing sequential output in a disk array storage device

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Maximizing sequential read streams while minimizing the...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Maximizing sequential read streams while minimizing the...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Maximizing storage system throughput by measuring system...

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
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Maximizing storage system throughput by measuring system...

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
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Maximizing throughput in a pairwise-redundant storage system

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Means to extend tTR range of RDRAMS via the RDRAM memory...

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
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Mechanism and apparatus allowing an N-way set associative...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Mechanism and method employing a plurality of hash functions...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Mechanism and method for cache snoop filtering

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Mechanism and method for cache snoop filtering

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Mechanism for automatic backups in a mobile system

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Mechanism for bank conflict resolution for an out-of-order...

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Mechanism for broadside reads of CAM structures

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Mechanism for collapsing store misses in an SMP computer system

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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