Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Patent
1998-09-11
2000-11-28
Yoo, Do Hyun
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
365 49, 712 14, 712 17, 382308, G11C 1500, G06F 1576
Patent
active
06154809&
ABSTRACT:
A two-dimensional PE (processing element) array that can achieve a small amount of hardware, short transfer time and high flexibility. It includes q.times.r CAMs, where q and r are any integers equal to or greater than two, and hit-flag lines. Each CAM has one-dimensionally arrayed w words, a hit-flag register capable of shift up and shift down, and an upper shift I/O port and a lower shift I/O port for inputting from and outputting to outside the contents of the hit-flag register. Each of the hit-flag lines connects the lower-shift I/O port of one of two horizontally adjacent CAMs with the upper-shift I/O port of the other of the two. The w words are arranged in m rows and n columns and are connected in a zigzag, and each word is assigned to a PE that performs various types of logical and arithmetic operations.
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Ikenaga Takeshi
Ogura Takeshi
Nippon Telegraph & Telephone Corporation
Portka Gary J.
Yoo Do Hyun
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