Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-10-16
2007-10-16
Nguyen, Hiep T. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
11054293
ABSTRACT:
A method, system, and computer program product for supporting multiple fetch requests to the same congruence class in an n-way set associative cache. Responsive to receiving an incoming fetch instruction at a load/store unit, outstanding valid fetch entries in the n-way set associative cache that have the same cache congruence class as the incoming fetch instruction are identified. SetIDs in used by these identified outstanding valid fetch entries are determined. A resulting setID is assigned to the incoming fetch instruction based on the identified setIDs, wherein the resulting setID assigned is a setID not currently in use by the outstanding valid fetch entries. The resulting setID for the incoming fetch instruction is written in a corresponding entry in the n-way set associative cache.
REFERENCES:
patent: 5651135 (1997-07-01), Hatakeyama
patent: 2005/0055506 (2005-03-01), DeMent et al.
Hrusecky David Allen
Levenstein Sheldon B.
Ronchetti Bruce Joseph
Saporito Anthony
Fay III Theodore D.
Gerhardt Diana R.
International Business Machines - Corporation
Nguyen Hiep T.
Yee Duke W.
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