Matching memory transactions to cache line boundaries

Details Matching memory transactions to cache line boundaries Matching memory transactions to cache line boundaries

2008-07-15

2008-07-15

Bragdon, Reginald G. (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S003000, C711S125000, C711S137000

Reexamination Certificate

active

07401184

ABSTRACT:
In general, in one aspect, the disclosure describes a method that includes generating multiple cache line accesses to multiple respective cache lines of a cache as required to satisfy an access to data specified by a single instruction of a processing element specifying an access to data.

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