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Livelock prevention by delaying surrender of ownership upon...

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Local memory management system with plural processors

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Lock caching for compound atomic operations on shared memory

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Lock control for a shared main storage data processing system

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Lock manager rotation in a multiprocessor storage area network

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Lock mechanism to enable atomic updates to shared memory

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Lock-up free data sharing

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Locked content addressable memory for efficient access

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Locking technique for control and synchronization

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Low latency lock for multiprocessor computer system

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Low latency memory access and synchronization

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Low latency memory access and synchronization

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Low latency request dispatcher

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Low latency request dispatcher

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Low latency request dispatcher

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Low occupancy protocol for managing concurrent transactions with

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Low overhead access to shared on-chip hardware accelerator...

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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