Limited virtual address aliasing and fast context switching with

Details Limited virtual address aliasing and fast context switching with Limited virtual address aliasing and fast context switching with

1997-05-23

2000-05-09

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

711203, 711202, 711 6, G06F 1200, G06F 1208

Patent

active

060617748

ABSTRACT:
Apparatus for supporting virtual address aliasing is disclosed in which addresses to a virtual cache are first intercepted. It is determined whether the these addresses are aliased, i.e., more than one virtual address exists for the same location in memory. If not aliased, the addresses are simply passed to the virtual cache. In the case where there is aliasing, however, dealiasing is performed. New addresses are generated and passed to the virtual cache so that the aliased addresses are directed to the same locations in the virtual cache. In this way, an operating system can be supported that uses virtual address aliasing since the CPU can transparently issue aliased virtual addresses. These addresses, however, are directed to the same locations in the virtual cache so that the addresses are not aliased from the perspective of the cache, thus avoiding the need for other hardware to compensate for the aliasing. The modification, however, does not substantially impact latency. The invention is most useful in situations in which the operating system merely requires the potential for aliasing between active processes.

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patent: 5680577 (1997-10-01), Aden et al.
patent: 5787474 (1998-07-01), Pflum
patent: 5802567 (1998-09-01), Liu et al.
patent: 5826057 (1998-10-01), Okamoto et al.

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