Burst data transfer to single cycle data transfer conversion and
Burst EPROM architecture
Burst mode cache with wrap-around fill
Burst mode data block transfer system
Burst signal generator
Bus access arbitration using unitary arithmetic resolution logic
Bus access control for a multi-host system using successively de
Bus activity sequence controller
Bus adapter module for interconnecting busses in a multibus comp
Bus adapter unit for digital processing system
Bus allocation synchronization system
Bus apparatus having hold registers for parallel processing in a
Bus arbiter
Bus arbiter with equitable priority scheme
Bus arbitrating circuit
Bus arbitration algorithm and apparatus
Bus arbitration and resource management for concurrent vector si
Bus arbitration scheme
Bus arbitration system
Bus arbitration system and method