Bus allocation synchronization system

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371 47, 371 61, 370 85, G06F 1516, G06F 1100

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active

042297923

ABSTRACT:
An improved bus allocation system to control a time division multiplexed digital data bus used by a plurality of signal sources such as a number of digital processing components in a decentralized system in which there is no single entity controlling the bus. The system includes a mechanism for maintaining allocation synchronization under realistic, non-ideal conditions in which noise or other error producing interferences may be present. Each signal source is provided with a bus interface unit having an address counter which operates in conjunction with an allocation vector. The counters operate through a repeating cycle of counts and one or more of the counts in each cycle based on its allocation vector. Each address counter is synchronized during or following the receipt of a message using a unique comparison sequence of comparisons. By means of this system the value of all counters within the range of synchronization are made identical in response to a bus allocation synchronization signal. If a given address counter is off too many counts to be synchronized, the transmitter of the associated device is disabled until it can be re-synchronized by a later synchronization signal. Thus any device having a counter that is out of synchronization for any reason cannot transmit until such synchronization is restored. This prevents interference occasioned by more than one device using the bus at a given time.

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