Bus arbiter with equitable priority scheme

Details Bus arbiter with equitable priority scheme Bus arbiter with equitable priority scheme

1987-07-06

1990-11-27

Chan, Eddie P.

Boots, shoes, and leggings

3642426, 3642428, 3642427, G06F 1336

Patent

active

049741489

ABSTRACT:
A bus arbiter for a multi-processor computer provides fair access by dynamically adjusting a base variable of a counter which is determined from a processor number of a previously access-requesting processor having the highest processor number. The counter then varies priority between a minimum processor number, such as zero, and the base variable of the counter. The priority signal from the counter and the current access-requesting processors are then provided to a memory device. The memory device is used to determine which current access-requesting processor is permitted to access the bus.

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patent: 4675812 (1987-06-01), Capowski et al.
patent: 4730268 (1988-03-01), Marin
patent: 4814974 (1989-03-01), Narayanan et al.

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