Jaime Humberto Moreno

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Apparatus region-based detection of interference among reordered

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Branch on cache hit/miss for compiler-assisted miss delay tolera

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Method and apparatus for reordering memory operations in a proce

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Object code compatible representation of very long instruction w

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Object-code compatible representation of very long instruction w

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
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Profile ID: LFUS-PAI-P-406281

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