Patent
1996-11-05
1998-05-26
Chung, Phung M.
39518503, 39518504, G06F 1134
Patent
active
057580510
ABSTRACT:
A computer processing system stores sequences of instructions in a memory for execution by a processor unit. An out-of-order load instruction may be created, either statically or dynamically, by moving a load instruction from its original position in a sequence of instructions to an earlier position in said sequence of instructions. Such out-of-order load instruction identifies a location in memory from which to read a datum and a first destination register in which to place the datum. The present invention is a method and corresponding apparatus that utilizes data comparison to detect coherence among memory and the datum read by an out-of-order load operation. More specifically, the method consists of an interference test which controls the processor unit to read a datum from the same location in memory identified by the out-of-order load instruction and compare the newly read datum with the datum saved in the first destination register. If the values do not match, the newly read datum is placed in a second destination register and a recovery sequence is executed. The second destination register may be identical to the first destination register. The invention is applicable to static and dynamic reordering of instructions, and can be implemented using instructions or using hardware resources.
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Moreno Jaime Humberto
Moudgill Mayan
Chung Phung M.
International Business Machines - Corporation
Sbrollini Jay P.
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