Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
Patent
1996-02-14
1999-09-14
Maung, Zarni
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate variable length...
712200, G06F 945
Patent
active
059516747
ABSTRACT:
Object-code compatibility is provided among VLIW processors with different organizations. The object-code can also be executed by sequential processors, thus providing compatibility with scalar and superscalar processors, A mechanism is provided which allows representing VLIW programs in an implementation-independent manner. This mechanism relies on instruction cache (I-cache) reload/access logic which incorporates implementation-dependent features into a VLIW program. In this way, programs are represented in main memory in an implementation-independent manner, the implementation-specific aspects are introduced as part of the instruction cache reload/fetch processes, and the simplicity in instruction dispatch logic that is characteristic of VLIW processors is preserved. The foregoing allows for object-code compatibility among VLIW processors with different organizations. Also provided is a mechanism and an apparatus for the interpretation of tree-instructions by a computer system based on a VLIW processor.
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International Business Machines - Corporation
Maung Zarni
Najjar Saleh
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