Method of making FUSI gate and resulting structure

Details Method of making FUSI gate and resulting structure Method of making FUSI gate and resulting structure

2006-10-05

2008-08-12

Nhu, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S663000, C438S692000, C438S680000, C438S311000, C257SE21170, C257SE21320, C257SE21082, C257SE21231, C257SE21416, C257SE21304

Reexamination Certificate

active

07410854

ABSTRACT:
Generally disclosed is a method of a device comprising forming a polysilicon stack including a first and a second polysilicon layer with an intervening etch stop layer, wherein the first polysilicon layer height is at least one third a height of the polysilicon stack height, removing the second polysilicon layer and the etch stop layer, and reacting the first polysilicon layer with a metal to fully silicide the first polysilicon layer. Fully silicided (FUSI) gates can hence be formed with uniform gate height. The thin first polysilicon layer allows for siliciding with a lower thermal budge and with better uniformity of the silicide concentration throughout the layer.

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Anil, K. G., et al., “CMP-less integration of Fully Ni-Silicided Metal Gates in FinFETs by simultaneous silicidation of the source, drain, and the gate using a novel dual hard mask approach,” 2005 Symposium on VLSI Technology Digest of Technical Papers, pp. 198-199.
Kittl, J. A., et al., “Scalability of Ni FUSI gate processes: phase and Vt control to 30 nm gate lengths,” 2005 Symposium on VLSI Technology Digest of Technical Papers, pp. 72-73.
Lauwers, A., et al., “CMOS Integration of Dual Work Function Phase Controlled Ni FUSI with Simultaneous Silicidation of NMOS (NiSi) and PMOS (Ni-rich silicide) Gates on HfSiON,” 2005 IEEE, 4 pgs.

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