Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-06-19
2004-02-03
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S763000, C438S787000, C438S792000
Reexamination Certificate
active
06686232
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an efficient method of fabricating semiconductor devices exhibiting high reliability with excellent uniformity and repeatability. The present invention has particular applicability in manufacturing high density, multi-level semiconductor devices with feature dimensions in the deep sub-micron regime.
BACKGROUND OF THE INVENTION
Silicon nitride deposition is employed extensively in various stages and in various aspects of semiconductor device fabrication. For example, a silicon nitride spacer is typically formed on side surfaces of a gate electrode during front end of the line (FEOL) processing, typically subsequent to ion implantation to form source/drain extension implants. Subsequent to silicon nitride spacer formation, a second dopant implantation is typically conducted to form moderately or heavily doped source/drain implants. The nitride spacers prevent dopants during the source/drain ion implantation from reaching the source/drain extensions, thereby maintaining the integrity of the lightly doped extensions.
As in other aspects of semiconductor fabrication, as the dimensions shrink into the deep sub-micron range, as in forming devices with a design rule of about 0.13 micron and under, it becomes necessary to reduce the thickness of the oxide liner and nitride sidewall spacers. However, as the thickness of such layers, typically deposited by plasma enhanced chemical vapor deposition (PECVD) decreases, it becomes increasingly difficult to obtain better process control, uniform thickness and high repeatability.
Accordingly, there exists a need for efficient methodology enabling the deposition of a layer silicon nitride at a reduced thickness with high quality, high uniformity and high repeatability.
SUMMARY OF THE INVENTION
An advantage of the present invention is a method of manufacturing a semiconductor device comprising depositing a silicon nitride layer at a low deposition rate with improved process control, high quality, high thickness uniformity within wafer and wafer-to-wafer, and excellent repeatability.
According to the present invention, the foregoing and other advantages are achieved, in part, by a method of manufacturing a semiconductor device, the method comprising depositing a layer of silicon nitride at a thickness of 100 Å or less by plasma enhanced chemical vapor deposition (PECVD) employing an ammonia (NH
3
) flow rate of 400 to 1200 sccm.
Embodiments of the present invention comprise depositing a silicon nitride layer at a silane (SiH
4
) flow rate of 50 to 100 sccm, a nitrogen (N
2
) flow rate of 2000 to 6000 sccm, a pressure of 0.8 to 1.8 Torr and an RF power of 200 to 600 watts, at an ultra low deposition rate of 400 to 600 Å/minute. Embodiments of the present invention include depositing the silicon nitride layer over an oxide layer formed on a gate electrode over a substrate with a gate dielectric layer therebetween, and etching to form a silicon oxide liner on side surfaces of the gate electrode and a silicon nitride liner/spacer on the silicon oxide liner. Embodiments of the present invention further include depositing the oxide liner layer at a thickness of 50 Å or less, and depositing the nitride spacer layer at a thickness of 100 Å or less, and in a plurality of deposition stages.
REFERENCES:
patent: 5731243 (1998-03-01), Peng et al.
patent: 5986329 (1999-11-01), Ngo
patent: 6080682 (2000-06-01), Ibok
patent: 6150286 (2000-11-01), Sun et al.
patent: 6156598 (2000-12-01), Zhou et al.
patent: 6207586 (2001-03-01), Ma et al.
patent: 6221793 (2001-04-01), Ngo et al.
patent: 6235654 (2001-05-01), Ngo et al.
patent: 6242367 (2001-06-01), Sun et al.
patent: 6399520 (2002-06-01), Kawakami et al.
patent: 2003/0132510 (2003-07-01), Barth et al.
Hopper Dawn
Huertas Robert A.
Ngo Minh Van
Pham Hieu
Advanced Micro Devices , Inc.
Jr. Carl Whitehead
Smoot Stephen W.
LandOfFree
Ultra low deposition rate PECVD silicon nitride does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Ultra low deposition rate PECVD silicon nitride, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Ultra low deposition rate PECVD silicon nitride will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3335170