Testing logic and embedded memory in parallel

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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C714S733000

Reexamination Certificate

active

07103814

ABSTRACT:
Technique to perform logic and embedded memory tests using logic scan chain testing procedures in parallel with memory built in self test (BIST). This is accomplished with a combination of voltage isolation between memory and logic segments, and isolation between logic and memory test clocks. A test algorithm is introduced to enable and disable the scan chain operation during BIST operation.

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