Testing apparatus and testing method for an integrated...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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C714S030000, C714S724000, C714S732000, C714S734000

Reexamination Certificate

active

10000089

ABSTRACT:
An apparatus enables a high quality test to be carried out within a short time, without forcing a severe design limitation on the designer and without an expensive tester. The apparatus includes a pattern generator built in an integrated circuit to generate pseudo random patterns as test patterns. A plurality of shift registers are configured with sequential circuit elements inside said integrated circuit. An automatic test pattern generating unit generates ATPG patterns. A pattern modifier modifies a portion, to which a predetermined value is required to be set in order to detect a fault, in said pseudo random patterns generated by said pattern generator, on a basis of said ATPG patterns, and inputs said modified pseudo random patterns to said shift registers.

REFERENCES:
patent: 5612963 (1997-03-01), Koenemann et al.
patent: 5991909 (1999-11-01), Rajski et al.
patent: 6061818 (2000-05-01), Touba et al.
patent: 6070252 (2000-05-01), Xu et al.
patent: 6070261 (2000-05-01), Tamarapalli et al.
patent: 6327687 (2001-12-01), Rajski et al.
patent: 6557129 (2003-04-01), Rajski et al.
patent: 6684358 (2004-01-01), Rajski et al.
patent: 6708305 (2004-03-01), Farnsworth et al.
patent: 6715105 (2004-03-01), Rearick
patent: 2002/0093356 (2002-07-01), Williams et al.
patent: 0 481 097 A11 (1992-04-01), None
patent: 57-116269 (1982-07-01), None
patent: 61-240173 (1986-10-01), None
patent: 63-83679 (1988-04-01), None
patent: 11-237450 (1999-08-01), None
patent: 2000-329831 (2000-11-01), None
Jas et al., “Hybrid BIST Based on Weighted Pseudo-Random Testing: a New Test Resource Partitioning Scheme”, IEEE Proceedings, VTS 2001, Apr. 29-May 3, 2001, pp. 2-8.
Barnhart et al., “OPMISR: The Foundation for Compressed ATPG Vectors”, IEEE Proceedings TC 2001, Oct. 30-Nov. 1, 2001.

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