Serial scan chain control within an integrated circuit

Details Serial scan chain control within an integrated circuit Serial scan chain control within an integrated circuit

2007-07-11

2010-06-08

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07734974

ABSTRACT:
An integrated circuit2includes a plurality of circuit blocks38, 40, 44each having an associated serial scan chain loop32, 34, 36which extends from a converter10, to the circuit block38, 42, 44in question and then back to the converter10. Multiplexing circuitry50, 52associated with each serial scan chain loop32, 34, 36is used to either include that serial scan chain loop32, 34, 36in a combined serial scan chain or to bypass that serial scan chain loop32, 34, 36. The circuit blocks38, 42, 44may be bypassed in this way if they are defective or if they are powered-down.

REFERENCES:
patent: 5423050 (1995-06-01), Taylor et al.
patent: 5428624 (1995-06-01), Blair et al.
patent: 5459737 (1995-10-01), Andrews
patent: 7165006 (2007-01-01), Dhong et al.
patent: 7580807 (2009-08-01), Bullock et al.
patent: 2005/0010832 (2005-01-01), Caswell et al.
Aerts et al., “Scan Chain Design for Test Time Reduction in Core-Based ICS”, IEEE International Test Conference, pp. 448-457 (1998).

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