Data processing architectures for packet handling wherein...

Details Data processing architectures for packet handling wherein... Data processing architectures for packet handling wherein...

2002-02-14

2010-12-21

Chan, Eddie P (Department: 2183)

Electrical computers and digital processing systems: processing

Processing architecture

Array processor

Reexamination Certificate

active

07856543

ABSTRACT:
A data processing architecture comprising:an input device for receiving an incoming stream of data packets; anda plurality of processing elements which are operable to process data received thereby;wherein the input device is operable to distribute data packets in whole or in part to the processing elements in dependence upon the data processing bandwidth of the processing elements.

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