Sequential in-situ heating and deposition of halogen-doped...

Details Sequential in-situ heating and deposition of halogen-doped... Sequential in-situ heating and deposition of halogen-doped...

2001-03-27

2002-04-23

Mills, Gregory (Department: 1763)

Coating apparatus

Program, cyclic, or time control

Having prerecorded program medium

C118S7230IR, C118S7230ER, C118S715000, C156S345420, C438S784000

Reexamination Certificate

active

06375744

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to the fabrication of integrated circuits. More particularly, the invention provides a technique, including a method and apparatus, for the deposition of a fluorine-doped insulating film having a reduced dielectric constant.
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called “Moore's Law”) which means that the number of devices which will fit on a chip doubles every two years. Today's wafer fabrication plants are routinely producing integrated circuits having 0.5 and even 0.35 micron feature sizes, and tomorrow's plants soon will be producing devices having even smaller geometries.
As device sizes become smaller and integration density increases, issues which were not previously considered important by the industry are becoming of concern. With the advent of multilevel metal technology in which three, four, or more layers of metal are formed on the semiconductors, one goal of semiconductor manufacturers is lowering the dielectric constant of insulating layers such as intermetal dielectric layers. Low dielectric constant films are particularly desirable for intermetal dielectric (IMD) layers to reduce the RC time delay of the interconnect metallization, to prevent cross-talk between the different levels of metallization, and to reduce device power consumption.
Many approaches to obtain lower dielectric constants have been proposed. One of the more promising solutions is the incorporation of fluorine or other halogen elements, such as chlorine or bromine, into a silicon oxide layer. Examples of halogen incorporation in films are described in U.S. patent application Ser. No. 08/548,391, filed Oct. 25, 1995 and entitled “METHOD AND APPARATUS FOR IMPROVING FILM STABILITY OF HALOGEN-DOPED SILICON OXIDE FILMS”, and Ser. No. 08/538,696, filed Oct. 2, 1995 and entitled “USE OF SIF
4
TO DEPOSIT F-DOPED FILMS OF GREATER STABILITY”, both of which are assigned to Applied Materials, Inc.
It is believed that fluorine, the preferred halogen dopant for silicon oxide films, lowers the dielectric constant of the silicon oxide film because fluorine is an electronegative atom that decreases the polarizability of the overall SiOF network. Fluorine-doped silicon oxide films are also referred to as fluoro silicate glass (FSG) films. The Ser. Nos. 08/548,391 and 08/538,696 patent applications each disclose formation of a plasma from a process gas that includes TEOS (Si(OC
2
H
5
)
4
) mixed with a helium carrier gas, oxygen (O
2
) and a fluorine source to deposit an FSG film. In illustrated embodiments of each application, the plasma is formed by the application of radio frequency energy to a pair of capacitively-coupled electrodes. Such a deposition method is referred to as plasma enhanced chemical vapor deposition (PECVD).
High density plasma (HDP) CVD reactors in which inductively coupled coils are employed to generate the plasma under very low pressure conditions (in the millitorr range) have also been used to deposit intermetal silicon oxide and FSG layers between closely spaced gaps on semiconductor structures. A plasma generated by such an HDP-CVD reactor has an ion density approximately two orders of magnitude or more greater than the ion density of a standard, capacitively coupled PECVD plasma. It is believed that the low chamber pressure employed in HDP-CVD reactors provides active species having a long mean free path. This factor, in combination with the density of the plasma, permits a significant number of plasma constituents to reach even the bottom portions of deep, tightly spaced gaps, and deposits a film with excellent gap-fill properties. Also, argon or a similar heavy inert gas is introduced into the reaction chamber to promote sputtering during deposition. It is believed that the sputtering element of HDP deposition etches away deposition on the sides of gaps being filled, which also contributes to the increased gap-fill of HDP-deposited films.
Some HDP reactors allow the plasma to be biased toward the substrate by the application of an electric field to further promote the sputtering effect. In one such reactor, the plasma is biased by application of RF energy from a bias RF (BRF) generator to an electrode in the chamber. Plasma formation in this reactor is formed by application of RF energy from a source RF (SRF) generator to a coil. The use of HDP-CVD reactors such as this is becoming increasingly important in the deposition of fluorine-doped silicon oxide intermetal dielectric layers.
In addition to decreasing the dielectric constant, incorporating fluorine in intermetal silicon oxide layers also helps solve common problems encountered in fabricating smaller geometry devices, such as filling closely spaced gaps on semiconductor structures. Because fluorine is an etching species, it is believed that fluorine doping introduces an etching effect on the growing film. This simultaneous deposition/etching effect allows FSG films to have improved gap filling capabilities such that the films are able to adequately cover adjacent metal layers having an aspect ratio of 1.8 or more.
Thus, manufacturers desire to include fluorine in various dielectric layers and particularly in intermetal dielectric layers. One problem encountered in the deposition of FSG layers is film stability. Loosely bound fluorine atoms in the lattice structure of some FSG films result in the films having a tendency to absorb moisture. The absorbed moisture increases the film's dielectric constant and can cause further problems when the film is exposed to a thermal process, such as an anneal process, during subsequent processing steps. The high temperature of such thermal processes can move the absorbed water molecules and loosely bound fluorine atoms out of the oxide layer through metal or other subsequently deposited layers. The excursion of molecules and atoms in this manner is referred to as outgassing. Such outgassing can be determined by detecting HF or H
2
O leaving the film as the film is heated to a specified temperature. It is desirable to have little or no outgassing at temperatures up to at least the maximum temperature used during substrate processing after the FSG film has been deposited (e.g., up to 450° C. in some instances).
Loosely bound fluorine atoms also tend to form hydrogen fluoride, a corrosive element which can attack metallization layers, forming gaps between the film and the metal. One solution to the problem of loosely bound fluorine atoms is to reduce the amount of fluorine used in a process gas. However, there is a correlation between the dielectric constant of an FSG film and the amount of fluorine in the process gas. Reducing the ratio of fluorine generally causes the dielectric constant of the resulting film to increase. Hence, it is desirable to include as much fluorine as possible in a film providing that other film qualities can be maintained within acceptable parameters.
From the above, it can be seen that it is desirable to produce oxide films having reduced dielectric constants. At the same time, it is also desirable to provide a method of increasing the stability of halogen-doped oxide films, thereby reducing moisture absorption and outgassing in the films.
Heat treatment steps in which a wafer is heated to a specified temperature for a specified time are employed for various reasons during substrate processing. For example, anneal steps are sometimes used to repair damage to a substrate after an ion implantation step or other processing step. Also, a brief heat treatment step has been employed to force absorbed water out of a layer such as a silicon oxide layer. The water degassing step is sometimes performed before deposition of an overlying diffusion barrier or metal layer to prevent the absorbed water from reacting with those layers during subsequent processing. As an example of this type of heat treatment step, a wafer ma

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