Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-06-03
2001-04-24
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S633000, C438S299000, C438S303000, C438S585000, C438S305000, C438S595000, C438S563000
Reexamination Certificate
active
06221704
ABSTRACT:
DESCRIPTION
1. Technical Field
The present invention is concerned with a method for fabricating field effect transistors (FETs) with shorter channels along with highly conductive gate. In particular, according to the present invention, the gate is provided employing a self-aligned conductive lithographic mask. According to the present invention, an image reversal technique employing a conductive refractory material as a self-aligned etching mask for defining the gate is employed.
2. Background of Invention
The FET is an important electrical switching device in large scale integrated circuits. Such circuits may contains hundreds of million of FETs on a single semiconductor chip. Such chips typically measure less than 1 cm on a side. The physical size (i.e. the lateral dimensions) of the FET device and the ease of electrically interconnecting a plurality of FETs are important factors in determining how closely devices may be packed into a given chip area. Thus, the degree of integration is in part determined by the device packing density.
The demands for higher performance MOSFET require MOSFETs to have shorter channel lengths for higher current drive. However, as the device channel length becomes shorter, the gate wiring width narrows. The narrowing of the gate wiring width, in turn, makes it difficult to process the gate for achieving low resistance such as by salicidation. Accordingly, work continues for providing new lithographic procedures for yielding the minimally smallest structure for a given lithographic features size without significantly increasing the complexity of the fabricating process. For instance, a technique referred to as hybrid resist lithography has been employed for manufacturing high performance device structure. In particular, such technique makes it possible to print sub-lithographic images along with excellent ACLV (Across Chip Line-Width Variation) control. However, current hybrid resist lithography provides only sub-lithographic images of “space” but not the “line” delineation.
SUMMARY OF INVENTION
The present invention provides a process for fabricating high performance devices exhibiting shorter channel lengths along with achieving highly conductive gate structures. The present invention takes advantage of hybrid resist lithography for achieving sub-lithographic “line” definition. According to the present invention, such is made possible by employing an image reversal technique that employs a highly conductive and refractory material as a self-aligned etching mask for defining the gate structure.
More particularly, the method of the present invention comprises providing a substrate; and forming isolation regions in the substrate. Next, a first insulating layer is formed on the isolation regions and on the substrate, followed by a first conductive-forming layer being formed on the first insulating layer. On the first conductive-forming layer, a second insulating layer is formed. Next, a resist layer is formed on the second insulating layer. An opening is created through the resist layer down to the second insulating layer and located vertically between the isolation regions formed in the substrate. The portion of the second insulating layer exposed by the opening is removed down to the conductive-forming layer. A second conductive material is deposited through the opening over the first conductive layer. The second insulating layer and the deposited second conductive material are planarized. The second insulating layer, the first conductive layer and the first insulating layer except that beneath the second conductive material are removed. The source and drain regions are then formed in the substrate.
An alternative method according to the present invention comprises providing a substrate; and forming isolation regions in the substrate. Next, a first insulating layer is formed on the isolation regions and on the substrate, followed by a first conductive-forming layer being formed on the first insulating layer. A second and different conductive layer is formed on the first conductive-forming layer. On the second conductive layer, a second insulating layer is formed. Next, a resist layer is formed on the second insulating layer. An opening is created through the resist layer down to the second insulating layer and located vertically between the isolation regions formed in the substrate. The portion of the second insulating layer exposed by the opening is removed down to the second conductive layer.
A third insulating material different from the second insulating material is deposited through the opening over the second conductive layer. The second insulating layer and the deposited third insulating material are planarized. The second insulating layer, the first and second conductive layers and the first insulating layer except that beneath the third insulating material are removed. The source and drain regions are then formed in the substrate.
According to preferred aspects of the present invention, the resist layer is a hybrid resist layer.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described only the preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.
SUMMARY OF DRAWINGS
FIGS. 1-4
are schematic diagrams illustrating a device in different steps of the fabrication process of the present invention.
FIGS. 5-8
are schematic diagrams illustrating an alternative structure in different steps of the fabrication process of the present invention.
FIG. 9
is a flow diagram of the sequence of fabrication steps employed according to the present invention.
REFERENCES:
patent: 4980317 (1990-12-01), Koblinger et al.
patent: 5496771 (1996-03-01), Cronin et al.
patent: 5700734 (1997-12-01), Ooishi
Furukawa Toshiharu
Hakey Mark C.
Holmes Steven J.
Horak David V.
Nakos James S.
Goodwin David
International Business Machines - Corporation
Pollock Vande Sande & Amernick
Shkurko Eugene I.
Wilczewski Mary
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