Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Multiple layers
Reexamination Certificate
2001-06-14
2003-01-28
Mulpuri, Savitri (Department: 2812)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Multiple layers
C438S781000, C438S778000, C438S931000, C438S798000
Reexamination Certificate
active
06511920
ABSTRACT:
BACKGROUND OF THE DISCLOSURE
1. Field of the Invention
The present invention relates to integrated circuits including interconnection structures and, more particularly, to a damascene structure defining conductive paths and/or vias between metal layers and a method of fabricating same.
2. Description of the Background Art
Integrated circuits have evolved into complex devices that can include millions of components (e.g., transistors, capacitors and resistors) on a single chip. The evolution of chip designs continually requires faster circuitry and greater circuit density. The demands for greater circuit density necessitate a reduction in the dimensions of the integrated circuit components.
As the dimensions of the integrated circuit components are reduced (e. g., sub-micron dimensions), the materials used to fabricate such components contribute to their electrical performance. For example, low resistivity metal interconnects (e.g., copper (Cu) and aluminum (Al)) provide conductive paths between the components on integrated circuits. Typically, the metal interconnects are electrically isolated from each other by an insulating material. When the distance between adjacent metal interconnects and/or the thickness of the insulating material has sub-micron dimensions, capacitive coupling potentially occurs between such interconnects. Capacitive coupling between adjacent metal interconnects may cause cross-talk and/or resistance-capacitance (RC) delay which degrades the overall performance of the integrated circuit.
In order to minimize capacitive coupling between adjacent metal interconnects, low dielectric constant bulk insulating materials (e.g., dielectric constants less than about 3.0) are needed. Examples of low dielectric constant bulk insulating materials include organosilicates, carbon-doped silicon oxides and carbon-doped fluorosilicate glass (FSG), among others.
In addition, a barrier layer often separates the metal interconnects from the bulk insulating materials. The barrier layer minimizes the diffusion of the metal from the interconnects into the bulk insulating material. Diffusion of the metal from the interconnects into the bulk insulating material is undesirable because such diffusion can affect the electrical performance of the integrated circuit (e.g., cross-talk and/or RC delay), or render it inoperative. Silicon carbide is often used as a barrier material in conjunction with low dielectric constant bulk insulating materials.
Some integrated circuit components may also include damascene structures. Damascene structures are multilevel interconnect structures that typically include two or more bulk insulating material layers and barrier layers stacked one on top of another. The multiple layers of bulk insulating material and barrier material are patterned to define vias and trenches through selected portions thereof. However, when organic or carbon-containing material layers are used for both the bulk insulating material and the barrier material, the etch selectivity of one to the other is poor using conventional fluorine-based etch chemistries. Poor etch selectivity between the bulk insulating material and the barrier material may undesirably form vias and trenches with larger than desired dimensions.
Therefore, a need exists for bulk insulating materials and barrier materials for use in damascene structures having good etch selectivity with respect to one another using conventional fluorine-based etch chemistries.
SUMMARY OF THE INVENTION
A method of forming an optical marker layer for etch endpoint determination in integrated circuit fabrication processes is provided. The optical marker layer is used in conjunction with organic and/or carbon-containing material layers that are useful as bulk insulating materials and barrier materials. The optical marker layer is formed on the bulk insulating material layer and/or the barrier material layer by incorporating an optical marker into the surface thereof. The optical marker is incorporated into the surface of the bulk insulating material layer and/or the barrier material layer by treating such layer with an optical marker-containing gas. The optical marker layer provides an optical marker emission spectrum when it is etched during a subsequent patterning step. Examples of suitable optical markers include nitrogen (N
2
), helium (He), argon (Ar), oxygen (O
2
), and combinations thereof.
The optical marker layer is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the optical marker layer is used to denote an etch endpoint between two organic or carbon-containing bulk insulating layers when fabricating a damascene structure. For such an embodiment, a preferred process sequence includes depositing a barrier layer on a metal layer formed on a substrate. After the barrier layer is deposited on the substrate a first bulk insulating layer is formed thereon. An optical marker layer is formed on the first bulk insulating layer. Thereafter, a second bulk insulating layer is formed on the optical marker layer. The second bulk insulating layer is patterned and etched down to the optical marker layer so as to define vias therein. After the vias are formed, the second bulk insulating layer is patterned to define interconnects therein. The interconnects are positioned over the vias previously defined therein, so as to transfer the vias through the first bulk insulating layer when the interconnects are formed in the second bulk insulating layer. Thereafter, the damascene structure is completed by filling the vias and interconnects with a conductive material.
Alternatively, the optical marker layer may be used to denote the etch endpoint between an organic or carbon-containing bulk insulating layer and an organic or carbon-containing barrier layer when fabricating a damascene structure. For such an embodiment, a preferred process sequence includes depositing a first barrier layer on a metal layer formed on a substrate. After the first barrier layer is deposited on the substrate, a first bulk insulating layer is formed thereon. A second barrier layer is formed on the first bulk insulating layer. An optical marker layer is formed on the second barrier layer. Thereafter, a second insulating layer is formed on the optical marker layer. The second bulk insulating layer is patterned and etched down to the optical marker layer so as to define vias therein. After the vias are formed, the second bulk insulating layer is patterned to define interconnects therein. The interconnects are positioned over the vias previously defined therein, so as to transfer the vias through the second barrier layer and the first bulk insulating layer when the interconnects are formed in the second bulk insulating layer. Thereafter, the damascene structure is completed by filling the vias and interconnects with a conductive material.
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Kim Yun-sang
Nguyen Huong Thanh
Xia Li-Qun
Yieh Ellie
Applied Materials Inc.
Moser Patterson and Sheridan
Mulpuri Savitri
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