Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
1998-10-19
2002-10-29
Whitehead, Jr., Carl (Department: 2823)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S763000, C438S786000, C438S906000, C438S958000, C438S964000
Reexamination Certificate
active
06472335
ABSTRACT:
BACKGROUND OF THE INVENTION
1) Field of the Invention
This invention relates generally to method for forming dielectric layers in a semiconductor device, more particularly to a method for improving the adhesion between inter metal dielectric (IMD) layers and more particularly to a HF dip etch to roughen the surface of an Oxide, SiN or SiON layer before an overlying low-K layer is formed.
2) Description of the Prior Art
To improve the RC delay in deep submicron technology, semiconductor manufactures need to implement low k (k value <3.0) dielectric materials and Cu interconnect materials. The inventors have found that dual damascene etching with low K materials has many challenges including low k profile control in etching and adhesion between underlying oxide layer (inter metal dielectric layer) and the overlying low k dielectric layer during photoresist polymer wet strip. Severe oxide dielectric layer peeling problems will induce the metal bridge after Cu chemical-mechanical polish and particles on wafers. This leads to shorting between Cu lines and other yield problems.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,482,894(Haveman) that shows a method of forming low-K dielectrics and an overlaying hard mask.
U.S. Pat. No. 5,708,303 (Jeng) shows a IDL method using Low-k materials and oxide layers.
U.S. Pat. No. 5,705,232(Hwang) shows a method of forming low-K dielectrics and an overlaying hard mask 34.
U.S. Pat. No. 5,561,318(Gnade et al) & U.S. Pat. No. 5,494,858(Gnade et al.) show a low-K dielectric between metal lines.
U.S. Pat. No. 5,723,383(Kosugi et al.) shows a H plasma treatment of a substrate surface.
U.S. Pat. No. 5,627,403(Bacchetta) shows an oxide adhesion layer (2 ) over a dielectric layer (4).
U.S. Pat. No. 5,767,582(Lee et al) shows an insulating layer treatment.
U.S. Pat. No. 5,658,994(Burgoyne, Jr. et al.) shows a PAE dielectric formula.
U.S. Pat. No. 5,759,906(Lou) and U.S. Pat. No. 5,559,055(Chang et al.) show examples of low-K dielectrics that can be used in the invention.
SUMMARY OF THE INVENTION
It is an objective of the present invention to provide a method for improving the adhesion between an underlying insulating layer (e.g., oxide, silicon nitride, SACVD) and an overlying low-K dielectric layer (e.g., Flare, PAE-2, FOX).
It is an objective of the present invention to provide a method for improving the adhesion between an underlying insulating layer (e.g., oxide, silicon nitride, Silicon oxynitride, SACVD) and an overlying low-K dielectric layer (e.g., Flare, PAE-2, FOX) by performing a HF dip etch on the insulating layer to roughen and improve the surface of the insulating layer.
It is an object of the present invention to provide a method for fabricating a inter metal dielectric (IMD) layer for a semiconductor device that do not peel when subjected to a photoresist strip.
It is an object of the present invention to provide a method for improving the adhesion between inter metal dielectric (IMD) layers and overlying Low-K dielectric layers between adjacent metal lines.
It is an object of the present invention to provide a method for to improving the adhesion between inter metal dielectric (IMD) layers by performing a HF dip etch to roughen the surface
14
of an Oxide, SiN or SiON insulating layer
14
before an overlying low-K layer
20
is formed.
To accomplish the above objectives and other objectives, the present invention provides a method improving the adhesion between inter metal dielectric (IMD) layers by performing a HF dip etch to prepare the surface of an Oxide, SiN or SiON insulating layer before a low-K dielectric layer is formed thereover. The present invention provides a method of fabricating a low-K IMD layer
20
over an oxide or nitride IMD layer
14
with improved adhesion. The invention's HF dip etch improves the adhesion between a 1st insulating layer
114
(oxide, SiN or SiON) and a low k dielectric layer
116
by preparing (e.g., roughening) the 1st insulating layer surface
16
. See FIG.
6
.
First, a first insulating (e.g., IMD) layer
14
is formed over a substrate. See
FIGS. 1
to
5
. Next, the invention's HF dip etch is performed on the 1st insulating layer
14
to form a treated surface
16
. Next, a second insulating layer
20
composed of a low-K material is formed over the prepared (e.g., rough) surface
16
of the first insulating layer
14
. The rough surface
16
improves the adhesion between a first insulating layer oxide (oxide, SiN or SiON) and a overlying low k dielectric layer by preparing the first roughening layer surface
16
. When subsequent photoresist etch and strip operations are performed (FIGS.
4
&
5
), the first insulating layer and 2nd insulating layer do not peel in subsequent photoresist strip processes.
Summary table: COMPOSITIONS OF THE LAYERS
preferred
layer
composition
alternate composition
1st insulating
SiO
2
Silicon oxynitride or SiN
layer 14
2nd insulating
Low-K
PAE2, SILK, poly(arlene ether)
layer (low-K)
material
(eg, Flare)
BENEFITS
The invention provides the following benefits:
the invention improves the adhesion between a oxide, SiN or SiON insulating layer
14
and an overlying low-K layer
20
between roughen the surface
16
of the layer
14
by a HF dip etch.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.
Additional objects and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of instrumentalities and combinations particularly pointed out in the append claims.
REFERENCES:
patent: 4744858 (1988-05-01), McDavid et al.
patent: 5373180 (1994-12-01), Hillenius
patent: 5482894 (1996-01-01), Havemann
patent: 5489553 (1996-02-01), Chen
patent: 5494858 (1996-02-01), Gnade et al.
patent: 5556806 (1996-09-01), Pan et al.
patent: 5559055 (1996-09-01), Chang et al.
patent: 5561318 (1996-10-01), Gnade et al.
patent: 5599746 (1997-02-01), Lur et al.
patent: 5627403 (1997-05-01), Bacchetta et al.
patent: 5635423 (1997-06-01), Huang et al.
patent: 5658994 (1997-08-01), Burgoyne, Jr. et al.
patent: 5705232 (1998-01-01), Hwang et al.
patent: 5708303 (1998-01-01), Jeng
patent: 5723383 (1998-03-01), Kosugi et al.
patent: 5731243 (1998-03-01), Peng et al.
patent: 5744391 (1998-04-01), Chen
patent: 5759906 (1998-06-01), Lou
patent: 5767582 (1998-06-01), Lee et al.
patent: 6046115 (2000-04-01), Molloy et al.
patent: 6121495 (2000-09-01), Babb
patent: 6143646 (2000-11-01), Wetzel
patent: 6207583 (2001-03-01), Dunne et al.
patent: 6235693 (2001-05-01), Cheng et al.
patent: 6288188 (2001-09-01), Godschalx
Wolf et al., “Silicon Processing for the VLSI Era, vol. 1”, Lattice Press, 1986, pp. 183, 192.
Cheng Yao-Yi
Tao Hun-Jan
Tsai Chia-Shiung
Ackerman Stephen B
Jr. Carl Whitehead
Saile George O.
Stoffel William J.
Taiwan Semiconductor Manufacturing Company
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